The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic apparatus, which performs wire bonding by laminating substrates.
High integration of semiconductor devices has been achieved in two dimensional LSI by the introduction of fine processes and improvements in package density. In recent years, a physical limitation of the refinements has started to be seen, and three dimensional LSI technologies have been gathering attention.
Bonding technology is a base technology in three dimensional LSI. There are a variety of systems within bonding technology, and technologies which bond chips to each other and technologies which bond wafers to each other have been considered. When a three dimensional LSI is fabricated by laminating device wafers together, there is a system of directly bonding Cu electrodes of the device side, which are formed on the wafer surface, with each other. In this system, there is a method which flattens the CU electrodes and an interlayer dielectric (ILD) so as to be on the same plane, and which performs hybrid bonding of Cu/ILD (Refer to JP 2006-191081A and JP H1-205465A). In such a bonding process, it may be necessary for the bonding surfaces to be extremely planar surfaces, in order to improve the bonding strength and to control bonding defects.